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Computer Architecture and Concurrency (COMP0008)

Key information

Faculty
Faculty of Engineering Sciences
Teaching department
Computer Science
Credit value
15
Restrictions
Module delivery for UG (FHEQ Level 5) available on BSc Computer Science; MEng Computer Science; MEng Mathematical Computation.
Timetable

Alternative credit options

There are no alternative credit options available for this module.

Description

Aims:

The module aims to provide a working knowledge of the hardware and architecture of a modern computer system, particularly focusing on concurrency aspects and those that have an impact on writing multithreaded software. Students will gain a fundamental understanding of the concurrency abstraction and how it impacts both computer architecture and software design. We will look at computer architecture aspects that directly impact multithreaded software such as the memory hierarchy, cache coherence/consistency and hardware multithreading. We will learn how to design correct multithreaded Java software based on a solid theoretical understanding of concurrency principles and the Java Memory Model. The module will cover an understanding of concurrency from low-level aspects (such as spin locks implemented in assembly language) to high-level design patterns used within the Java concurrency package.

Intended learning outcomes:

On successful completion of the module, a student will be able to:

  1. Use the concurrency abstraction to reason about concurrent systems.
  2. Write and understand modern assembly language programs.
  3. Describe how high-level languages are translated to assembly language and subsequently machine code.
  4. Describe the internal structure of processors and different forms of parallelism employed.
  5. Describe how modern computers handle memory and input/output including key concurrency aspects such as cache coherence, memory consistency/visibility and interrupt-driven thread switching.
  6. Describe how operating systems schedule application level threads onto the CPU resources.
  7. Describe how synchronization mechanisms in high-level languages are implemented in terms of more primitive hardware concurrency instructions.
  8. Reason about and resolve safety aspects of multithreaded Java including interference and visibility issues.
  9. Write safe and efficient multithreaded Java code using the monitor design and other patterns.
  10. Compare and contrast the traditional Java concurrency mechanisms with those of the new Java concurrency package mechanisms.
  11. Correctly and safely use the thread-safe data and control structures within the new Java concurrency package.

Indicative content:

The following are indicative of the topics the module will typically cover:

  • Top-down high level overview of a computer: the main components making up a computer and how they interact.
  • The concurrency abstraction.
  • Assembly language and machine code.
  • Translation of high-level languages into machine code.
  • Internal structure of a processor: the control unit (CU) and datapath.
  • Parallelism within the CPU.
  • Key aspects of how operating systems handle application-level threads.
  • Memory hierarchy, cache structure and cache coherence mechanisms.
  • Creating and managing Java threads.
  • Understanding and reasoning with the Java Memory Model (JMM) specification.
  • Java traditional synchronization mechanisms (and how they relate to low-level hardware instructions)
  • Monitor design patterns and conditional variables.
  • Reasoning about the correctness of concurrent programs: safe data structures.

Requisites:

To be eligible to select this module as optional or elective, a student must: ​(1) be registered on a programme and year of study for which it is a formally available; (2) understand basic computer arithmetic (binary/hex manipulation, fixed-size arithmetic, 2s- and 16s-complement forms, etc.); and (3) have strong Java programming skills.

Module deliveries for 2024/25 academic year

Intended teaching term: Term 1 ÌýÌýÌý Undergraduate (FHEQ Level 5)

Teaching and assessment

Mode of study
In person
Methods of assessment
100% Fixed-time remote activity
Mark scheme
Numeric Marks

Other information

Number of students on module in previous year
0
Module leader
Dr Stefano Vissicchio
Who to contact for more information
cs.undergraduate-students@ucl.ac.uk

Last updated

This module description was last updated on 8th April 2024.

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